Huffman-based code compression techniques for embedded systems

Increasing embedded systems functionality causes a steep increase in code size. For instance, more than 60MB of software is installed in current state-of-the-art cars [9]. It is often challenging and cumbersome to host vast amount of software in an efficient way within a given hardware resource budget of an embedded system. This may be done by using code compression techniques, which compress the program code off-line (i.e. at design time) and decompress it on-line (i.e. at run time). Among all statistical compression algorithms, Huffman Coding is one of the best compression techniques since it provably provides the shortest average codeword length [36]. When Huffman Coding is used as a compression technique, Look-up Table(s) are generated to store the original instructions. As the size of the tables becomes large, it may negatively affect the final compression ratio (defined as the ratio of compressed code to uncompressed code). Thus, the Look-up Tables diminish the advantages that could be obtained by compressing the code. This thesis presents different Huffman-based hardware supported code compression techniques, which can efficiently solve this problem and improve the compression ratio. In addition to that, this the presents a new technique to improve the performance of the hardware decoder. The code compression techniques are targeted two processor architectures, namely RISC and VLIW. In this thesis, the Look-up Table size is reduced by using the “Look-up Table Compression Technique” for RISC processors. This is done by sorting the entries of the table to decrease the number of bit toggles between each two successive entries. To show the efficiency of the “Look-up Table Compression Technique”, we apply it to two compression schemes, i.e. Dictionary-based Compression Scheme and Statistical Compression Scheme. Using the “Look-up Table Compression Technique” reduces the table size by up to 45% and improves the compression ratio on average by more than 25%. The evaluations are conducted using a representative set of applications from MiBench [20] and are built for three major embedded processor architectures, namely ARM, MIPS viii