ISSCC 2006 / SESSION 32 / PLLs , VCOs , AND DIVIDERS / 32 . 2 32 . 2 A 0 . 5 to 2 . 5 GHz PLL with Fully Differential Supply - Regulated Tuning

PLLs are important building blocks that are used to generate and distribute clocks in all high-performance digital systems. Integrating PLLs on large digital chips in deep submicron processes poses three main challenges. First, power supply noise caused by increased digital switching currents degrades the jitter performance of the VCO. Second, the wide loop bandwidth required to suppress ring oscillator noise exacerbates the phase noise caused by charge-pump noise. In particular, the flicker noise in short-channel-length devices dominates the overall inband noise. Finally, the need to integrate many clock-distribution PLLs on a single chip mandates that they each occupy a small area. This paper describes a PLL that alleviates power supply noise through the use of a fully differential supply-regulated tuning method and suppresses charge-pump flicker noise by using a passive resistor in place of a conventional active current source. A ring VCO is used rather than an inductor-based VCO to satisfy die area constraints. The PLL operates over a wide frequency range (0.5 to 2.5GHz) with 3.29ps rms jitter at 2.4GHz and consumes 25mW from a 1.8V supply.