Coordinated Management: Power, Performance, Energy, and Temperature

We are developing a next-generation power manager that supports high performance within the constraints of limited power, energy, and temperature levels. To date, we have developed simulation infrastructure to model a technology-scaled version of an Alpha 21364 processor and have added three independent management techniques to the simulator model. One technique dynamically scales frequency and voltage settings. Another technique, pipeline throttling, restricts the rate of integer instruction issue. The third technique reduces leakage power in caches while retaining memory contents. We are currently using the simulation infrastructure to gauge the effect of management techniques. This report provides an overview of our research project and summarizes the current status of this work.