Fault Tolerant , Low Voltage SRAM Design

Scaling of process technologies has made power management a significant concern for circuit designers. Moreover, denser integration and shrinking geometries also have a negative impact on circuit reliability. Therefore, fault tolerance is becoming a more challenging problem. Static Random Access Memories (SRAMs) play a significant role in circuit power consumption and reliability of digital circuits. This thesis focuses on fault tolerant and low voltage SRAM design. A double error correcting binary BCH codec is chosen to mitigate reliability problems. Different decoding schemes are compared in terms of their synthesized power, area and latency. An alternative decision-tree based decoder is analyzed. This decoder requires 16ns for error correction and 5ns for error detection at 1.2V using 65nm CMOS. Compared to conventional iterative decoding scheme in which error correction takes more than 100 clock cycles for 128-bit word length, the analyzed decoder has a significant latency advantage. Meanwhile, compared to the look-up table (LUT) decoder, the decision-tree based architecture has 2X area and power savings. Hence, the tree-based decoder is an alternative design which does not have the extreme power and area consumption of a LUT decoder and does not have the extreme latency of an iterative implementation. An 8T SRAM block is designed in 65nm CMOS low-power, high VT process for the on-chip caches of a low-voltage processor. This SRAM is designed for the array voltage range of 1.2V to 0.4V. It provides more than 4 orders of magnitude performance scaling and lOX power savings. Thesis Supervisor: Anantha P. Chandrakasan Title: Joseph F. and Nancy P. Keithley Professor of Electrical Engineering