A Maximum Time Di erence Pipelined Multiplier
نویسنده
چکیده
The maximum time diierence pipelining is an eeective way to increase the clock rate of a circuit. The maximum time diierence pipelined 8 8 2's complement multiplier based on a 1:5m semi-custom HCMOS process discussed in this paper can work nearly three times faster than an ordinary multiplier based on the same technology. Test result shows the majority of the multiplier's time diierence is caused by data-dependent delay variation which is the inherent shortcoming of the semi-custom process. Therefore the potential advantage of maximum time diierence pipelining can be further explored with a custom CMOS design.
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