Linear Timing Analysis of Soc Synchronous Circuits with Level-sensitive Latches
نویسندگان
چکیده
This paper describes a linear programming (LP) formulation applicable to the timing analysis of large scale SOC synchronous circuits with level-sensitive latches. The proposed formulation uses a variation of the big M method [1] to modify the nonlinear constraints in the problem formulation into solvable linear constraints. By making maximum use of cycle stealing [2], operation at a higher clock frequency (reduced clock period) is possible. The industrial LP solver CPLEX [3] is used on the ISCAS’89 benchmark circuits demonstrating significant improvements in clock period.
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