Digitally Controlled Delay Lines Based On NAND Gate for Glitch Free Circuits

The traditional analog signal processing is expected to progressively substituted by the processing times of the digital domain in the VLSI .Within this novel paradigm ,digitally controlled delay lines should play the vital role in the digital-toanalog converters ,and in analog intensive circuits. From a practical point of view, nowadays, DCDL is a key block in the many applications like All Digital Phase Locked Loop, All Digital Delay Locked Loop, All Digital Spread Spectrum Clock Generator, etc. The classical method to design the DCDL is mostly based on the AND delay units and a MUX to select the output so called MUX based DCDL. Other designs are tree based MUX delay unit, inverter based, NAND based delay elements. The NAND based DCDL produce glitches which limit their employability in many applications. In most common application DCDL is used to process the clock signal, therefore glitch free DCDL operation is required. In this paper NAND based DCDL present the glitch free circuits by the control switching of the delay control codes. The proper driving circuits are also designed to drive the control bits to the DCDL with the timing constrain for the delay control code. The proposed DCDL has the same resolution and minimum delay of the previously existing DCDL. The proposed glitch free DCDL is implemented in the ADDLL for the verification that confirms the correctness of the designed glitch free DCDL. Keywords— digitally controlled delay lines (DCDL), All digital delay locked loop (ADDLL), All digital phase locked loop (ADPLL), Spread-spectrum clock generator (SSCG).