Using DMAIC Methodology for MLP Reflow Process Optimization

The widely publicized and studied implementation of lead free solders has led to increased scrutiny on the solder joint formation for surface mount technology electronic components. During the lead free transition packaging technology for power semiconductor components increasingly embraced molded leaded package (MLP) technology. Due to the application demands of power devices, namely temperature control and reliability, many end users have placed considerable emphasis on process void minimization. Experiments have shown that increasing the quantity of solder paste printed will often minimize process voiding, but incidences of solder balling and beading often increase. Due to their comparative complexity, multi-die MLPs have shown to be more sensitive to solder process design and control. This created the need for a thorough investigation of solder process parameters, and a method to collect and analyze the data from a set of experiments to optimize the process. No previous process found by the experimenters was found to meet the needs of the problem. Demonstrated in this paper is a six sigma based methodology for developing a rigorous design of experiments for determining the best process for surface mounting a 6x6 DrMOS MLP component. Critical factors will be identified and treated statistically using DMAIC methods. Introduction The use of six sigma tools and processes has allowed companies to take many aspects of their businesses to the next level. As a toolset, six sigma methodologies were originally forged in the furnace of manufacturing. This makes the methodologies particularly applicable to surface mount process optimization. Concurrently, there have been many advances in power semiconductor packaging and applications technology. The insatiable demand for both miniaturization and increased feature sets in consumer electronics has lead to a need for power semiconductor devices to increase power handling and improve power density in designs. With this trend, Intel created specifications for 6x6mm DrMOS products, power semiconductor devices that see the copackaging of a MOSFET gate driver IC, and the high and low side MOSFETs used for synchronous power rectification commonly employed in computing applications. This specification is specific that there are to be three Die Attach Pads (DAPs) and 40 external pins for I/O. Devices based on this specification (though not always complying) often have maximum current ratings in excess of 30 amperes, and switch at frequencies up to and exceeding 1 megahertz. This places a demand on the system for excellent thermal and electrical performance, necessitating high performance execution from circuit to board to reflow process design. Many engineers and technicians have applied six sigma tools to electronics manufacturing. A search of the literature however did not show many results for applying this methodology to a multi-DAP MLP package which provide their own unique challenges. This paper will demonstrate how to quickly optimize the reflow process for a multi-DAP package, but the methodology will be applicable to any package type. Power semiconductor suppliers often are requested to support customers at many steps of the design process. As a new design ramps up through qualification builds, the customer may ask the component supplier to help with the optimization of the surface mount process. This can be a very time sensitive request, and is often at a critical juncture in the new product phase for the customer, initial ramp to release. As delays at this point can become widely publicized and commensurately costly, often the customer needs resolution to what can be a difficult problem with interaction effects of both their manufacturing site and the component, very quickly. Correct application of six sigma tools and methodologies can allow for the handling of large designs of experiments and statistical analysis, with production improvements able to follow rapidly. The organization the tools provide to the data allows for faster design of experiment (DOE) turn-around times, and improved customer acceptance of changes to their process. The Challenge Every project starts with the formation of a team to solve a specific problem. The problem initiating study here was a 6x6 DrMOS ready to go to market experiencing low, but persistent, levels of solder beading created during reflow as a customer was completing qualification builds for an important new product for their company. As originally published in the IPC APEX EXPO Conference Proceedings.