Delay testing considering power supply noise effects

We propose a new delay test generation technique that can take into account the impact of the power supply noise on the signal propagation delays. This is di erent from existing delay fault models and test generation techniques that ignore the dependence of path delays on the applied test patterns and cannot capture the worst-case timing scenarios in deep submicron designs. In addition to sensitizing the fault and propagating the fault e ects to the primary outputs, our new tests also produce the worst-case power supply noise on the nodes in the target path. Thus, the tests also cause the worst-case propagation delay for the nodes along the target path. Our experimental results on benchmark circuits show that the new delay tests produce signi cantly longer delays on the tested paths compared to the tests derived using existing delay testing methods.