A Glitch in the Theory of Delay - Insensitive Circuits

There is a questionable assumption made in the theory and practice of delay-insensitive circuits, as presented by Dill Dil88b] and Burns and Martin BM88]. The problem is illustrated by the following puzzle. Puzzle: Consider an OR gate (see Figure 1) with inputs labeled a and b, and an output labeled c. Suppose that the circuit initially has a = 1, b = 0 and c = 1; The b input then rises, and then some nite positive time later, a drops. Does output c glitch? 2 Figure 1: An OR gate. The inputs are labeled a and b. The output is labeled c. The answer to this puzzle depends on your assumptions about the OR gate. Dill's veriier and Martin's translator both assume that c does not glitch in this case. Our position is that c does glitch. We will refer to this class of glitch as an internal glitch. (By glitch, we mean that the circuit produces an unpredictable output, and possibly enters an unpredictable state. We will discuss glitches in more detail and with more care later in the paper.) This paper investigates the puzzle of this new glitch, in the following linear, self-timed sequence of events. The introduction is presented (you are almost done reading it). We review the work of Martin and of Dill, with an eye to understanding what kinds of glitches are avoided by Martin's designs, and what kind certiication Dill's veriier makes of circuits. We also demonstrate that Martin's circuits and Dill's veriier both make the assumption that the internal-glitch is not a problem. We show that the internal-glitch really can be a problem, by demonstrating two implementations of OR gates (implemented at diierent levels of abstraction), both of which suuer from internal-glitches. We explore three diierent xes to the internal-glitch problem. The xes include ignoring the problem, xing the problem, and exploiting the problem to build even better circuits. We demonstrate our xes on a few selected circuits. We conclude with a summary and some directions for future work. 2 A remark on notation: This paper uses the value 0 to indicate the logical value FALSE, and the value 1 to indicate the logical value TRUE.