Performance Analysis of Dual Gate Mosfet in Parallel Adder

This paper describes a parallel single-rail self-timed adder using dual gate MOSFETs which builds on a recursive formulation for performing multibit binary addition. Thus the addition is equivalent for those bits that do not need any carry chain propagation and the circuit attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A real design of dual gate MOSFET is provided along with a completion finding unit. The design is regular and does not need any real limitations of high fan outs. A high fan-in gate is necessary on the design but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been executed using LT spice tool that verify the practicality and superiority of the proposed approach over existing asynchronous adders.