Design of Low Power Barrel Shifter and Rotator Using Two Phase Clocked Adiabatic Static Cmos Logic
نویسندگان
چکیده
This paper presents low power operation of barrel shifter and rotator which are designed and simulated in 2 phase clocked adiabatic static CMOS logic. The power consumption of the circuits is compared with that of static CMOS logic. A barrel logic right shifter, a right rotator and shift/rotator are simulated in 45nm CMOS process technology. A mux based design is used for all the above circuits. The 2PASCL circuits are observed to have low power consumption while compared to circuits which are simulated using static CMOS logic. The power consumption of 2PASCL circuits are reduced by 69.67% compared to static CMOS logic. From the simulation results it is observed that the logic circuits which use 2PASCL logic can be used for low power applications.
منابع مشابه
Design of 32×32 Barrel Shifter Using Various Adiabatic Techniques for Low Power Applications
Now a day’s technology enhancement is at a blistering pace. Merely VLSI has a meteoric rise due to the adoption of new techniques. Static CMOS had a limitation of deploying constant power supply. Less power dissipation is an essential attribute for any optimized design. Varying the power supply is the very thing for preventing the power dissipation. An adiabatic logic is a new technique to redu...
متن کاملDesign and Analysis of Conventional CMOS and Energy Efficient Adiabatic Logic for Low Power VLSI Application
In recent years, low power circuit design has been an important issue in VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. energy. This paper proposes an Adder circuit based on energy efficient two-phase clocked adiabatic logic. A simulative investigation on the proposed 1-bit ful...
متن کاملLow-Power 4×4-Bit Array Two-Phase Clocked Adiabatic Static CMOS Logic Multiplier
The present study evaluates four designs of XOR using our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for a 4ˆ4-bit array 2PASCL multiplier. Based on simulation results obtained using 0.18 —m standard CMOS technology, at transition frequencies of 1 to 100 MHz, the 4ˆ4-bit arra...
متن کاملTwo Phase Clocked Adiabatic Static CMOS Logic and its Logic Family
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to Vdd. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output ...
متن کاملStudy and Comparison of Two Phase Clocked Adiabatic logic (2PASCL) for Low Power VLSI Applications: A Review
As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a concern in the design of VLSI circuits. This paper presents a Two-Phase Adiabatic Static Clocked Logic (2PASCL) which shows the lowest power dissipation among different adiabatic logic families based on energy recovery principle. In adiabatic switching ...
متن کامل