Delay Optimization of Low Power Reversible Gate using MOS Transistor Level design

In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce energy loss due to the information bits lost during the operation information loss occurs because the total number of output signals generated is less than total number of input signals applied. In reversible if the input vector can be uniquely recovered from the output vector and if there is a one to one correspondence between its input and output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future in design of low power consumption circuits and high speed application.