Towards an Optimal Implementation of MLP in FPGA
نویسندگان
چکیده
We present the hardware implementation of partially connected neural network that is defined as an extended of the MultiLayer Perceptron (MLP) model. We demonstrate that partially connected neural networks lead to a higher performance in terms of computing speed (requiring less memory and computing resources). This work addresses a complete study that compares the hardware implementation of MLP and a partially connected version (XMLP) in terms of computing speed, hardware resources and performance cost. Furthermore, we study also different memory management strategies for the connectivity patterns.
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