High-Speed Low-Power Complex Matched Filter for W-CDMA: Algorithm and VLSI-Architecture

High-speed low-power matched filter plays an important role in the fast despreading of spread-signals in wideband code division multiple access (W-CDMA) mobile communications. In this paper, we describe the algorithm and the VLSIarchitecture of a complex matched filter chip implemented by our proposed digital-controlled analog parallel operational circuits. The complex matched filter VLSI with variable taps from 4 to 128 is developed for despreading QPSK-modulated spread-signals for W-CDMA communications, which is fabricated by a 2-metal 0.8μm CMOS technology. The dissipation power of the chip is 225mW and 130mW when it operates at the chip-rate of 20MHz with the supply voltages of 3.0V and 2.5V, respectively, and it can be furthermore reduced to 62mW at chip rate of 10MHz when the supply voltage is lowered to 2.2V. The 3-dB cut-off frequency of the fabricated chip is higher than 20MHz for both 3.0V and 2.5V supplies. Comparing to pure digital matched filters, the massive and high-speed despreading operations of the spread-signals are directly carried out in analog domain. As a result, two high-speed analog-to-digital (A/D) converters operating at chip rate are omitted, the inner signal paths and the total dissipation power are greatly reduced. key words: weighted-sum operation, parallel analog operational circuit, mixed-signal LSI, matched filter