Modeling and Simulation of High Level Leakage Power Reduction Techniques for 7T SRAM Cell Design

In this paper, the process of 7T SRAM cell is analyzing and also exploring the circuit topologies, high level leakage power reduction techniques and cell parameters. The first segment contains the information about process of the 7T SRAM cell like write operation and read operation. Second segment of this paper characterize high level the leakage power reduction techniques, containing the information about how many types of techniques are available for characterizing the high level leakage power reduction techniques and what is the effect on the high level leakage power reduction techniques on 7T SRAM cell design. The third segment of this paper shows the information about cell parameters means how many parameters we use to describe our circuit. This segment of the paper is the most important segment because this segment contains the information about all the parameters of 7T SRAM cell. In the second segment of this paper contains the information about high level leakage power reduction techniques, by using high level leakage power reduction techniques we can make our 7T SRAM cell much better in different area like power dissipation, leakage power reduction, short circuit power consumption, dynamic power consumption, cell write delay, cell read delay, static noise margin. The data of leakage power consumption shows that after voltage scaling technique leakage power consumption and dynamic power consumption is less.