A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers
نویسندگان
چکیده
characteristics of multi-bit CMOS adders. Lemonds et al. The design of portable battery-operated systems requires multiplication circuits of low switching activity. This paper studies multiplication algorithms, sign extension methods, adding structures, resource sharing and component [81 Proposed to use synchronization latches in multiplier m a y to reduce race glitches. Techniques for lowering the switching activity of combinational PLA circuits were presented by Hossainf et al. in 191. schematic aternatives from the point of decreasing ihe total number of logic transitions in the target multiplication circuit. Experiments show, that by utilizing the signeddigit encoding scheme, modified sign extension technique, 4-2 adding compressors and swing restored transistor path logic, a twice as low switching activity can be achieved.
منابع مشابه
Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
متن کاملModified 32-Bit Shift-Add Multiplier Design for Low Power Application
Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...
متن کاملEmpirical Review of Low Power Column by Pass Multiplier
Designing high-speed multipliers with low power and regular in layout have substantial research interest. The analysis is done on the basis of certain performance parameters i.e. Area, Speed and Power consumption and dissipation. Multipliers are considered to be an important component in DSP applications like filters. Therefore, the low power multiplier is a necessity for the design and impleme...
متن کاملLow Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition
A novel low power multiplication algorithm for reducing switching activity through operand decomposition is proposed. Our experimental results show 12% to 18% reduction in logic transitions in both array multipliers and tree multipliers of 32 bits and 64 bits. Similar results are obtained for dynamic power dissipation after logic synthesis. One additional logic gate is required on the critical ...
متن کاملLow Power Multiplier Design Using Latches and Flip-Flops
Problem statement: Power dissipation is designated as critical parameter in modern VLSI design field. In VLSI implementation low power concept is necessary to meet Moore’s law and to produce consumer electronics with more back up and less weight. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power which is the major part of power dissipatio...
متن کامل