Reliability and Characteristics for Wafer Level Chip Scale Packages under Current Stressing

This work presents a novel approach and method for examining the characteristics of wafer-level chip-scale packages (WLCSPs) for electro migration (EM) tests. The die in the WLCSP was directly attached to the substrate via a soldered interconnect. The die shrinks area available for power and the solder bump also shrinks volume and increase quantity of electron for interconnect efficiency. The bump current density now approaches 10 A/cm, at which point the electromigration (EM) becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness and others. New interconnection geometry has been used utilized extensively with moderate success in overcoming larger mismatches in components displacements during current and temperature excursions. Both the environments and testing qualifications for these packages are becoming increasingly more and more demanding. Failure mechanisms once considered eliminated, or at least reduced to a manageable extent in new package technology designs, are again challenging process integrity and reliability. Especially for WLCSPs, which were first designed to eliminate any need for encapsulation to be compatible with the smart-mount technology (SMT) process, and to have good handing properties face serious reliability problems? This study investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125C. A reasonably strong correlation existed between mean-time-to-failure (MTTF) of the WLCSP test vehicle and the average current density carried by a solder joint was obtained. A series of current densities were also applied on to WLCSP architecture; Black’s power law was utilized to simulate for the failure mode analysis. Furthermore, SEM was implemented to determine which levels differences were existed between high and low current density failure modes.