Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design

A graph-based approach is presented for the generation of exact symbolic network functions in the form of rational polynomials of the complex frequency variable for analog integrated circuits. The approach employs determinant decision diagrams (DDDs) to represent the determinant of a circuit matrix and its cofactors. A notion of multiroot DDDs is introduced, where each root represents a symbolic expression for an individual coefficient of the powers of in the numerator and denominator of a network function, and multiple roots share their common subgraphs. A DDD-based algorithm is presented for generating -expanded network functions. We prove theoretically and validate experimentally that the algorithm constructs in ( DDD ) time an -expanded DDD with no more than DDD vertices, where is the degree of the denominator polynomial, is the maximum number of devices that connect to a circuit node, and DDD is the number of DDD vertices representing the circuit-matrix determinant. For a practical circuit, DDD is often many orders-ofmagnitude less than the number of product terms. In contrast, previous approaches require the time and space complexities proportional to the number of product terms, which grows exponentially with the size of a circuit. Experimental results have demonstrated that the new approach can produce exact -expanded-symbolic network functions for A741 operational amplifiers in several CPU seconds on an UltraSparc-I workstation. The expressive power of multiroot -expanded DDDs is so remarkable that in one instance, over 10 symbolic product terms have been represented by a multiroot DDD with less than 17 K vertices. The compactness of DDDs is further demonstrated in the context of symbolic noise evaluation, where potentially many transfer functions, each being used for a noise source in the circuit, can be represented by a single DDD with the size comparable to that for a few transfer functions. This provides a powerful tool for solving many symbolic analysis problems such as deriving interpretable symbolic expressions, dominant pole/zero estimation, and analog testability analysis. We have also demonstrated that repetitive numerical evaluation with the derived -expanded symbolic expressions for frequency-domain simulation and small-signal noise analysis can be much faster than SPICE-like simulators and the resulting expressions for a circuit block can be used as behavioral models for high-level simulation. Manuscript received December 22, 1999; revised October 31, 2000. This work was supported by the Defense Advanced Research Projects Agency, United States Air Force, Wright Laboratory, Manufacturing Technology Directorate, under Grant F33615-96-1-5601, by a National Science Foundation CAREER Award, and by Conexant Systems. This paper was presented in part at the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1998, and the Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 2000. This paper was recommended by Associate Editor K. Mayaram. C.-J. R. Shi is with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195 USA (e-mail: [email protected]). X.-D. Tan was with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195 USA. He is now with Monterey Design Systems, Sunnyvale, CA 94089 USA. Publisher Item Identifier S 0278-0070(01)04826-6.