High Level Synthesis for Designing Custom Computing Hardware

We examine the application of High Level Synthesis to FPGA based computing systems. Our experience shows that high level synthesis allows for a level of design space exploration unrealizeable with register transfer level techniques. In addition, the use of high level tools allow designers to prototype their designs with high quality results and fast design turn around times. Our design ow makes use of the Synopsys Be-havioral Compiler followed by logic synthesis to map designs onto the Altera RIPP10 board. We discuss our experiences with a case study: designing a DTMF receiver from a high-level behavioral description down to implementation on the RIPP10 board. Using our design ow, we were able to design working hardware, meet our delay constraints, and achieve 90% utilization of the available FPGAs. In the process, we examined close to 100 diierent RTL designs. The nal design had approximately 90,000 gate equivalents.