High Throughput LFSR Design for BCH Encoder using Sample Period Reduction Technique for MLC NAND based Flash Memories

Error correction is one of the important technique for detecting and correcting errors in communication channels, memories etc. , Errors are associated with all types of memories. But the NAND FLASH memories are competing in the market due to its low power, high density, cost effectiveness and design scalability. As far as the memory is concerned the testing should not consume more time. So, some DSP algorithms are used to overcome the delays by increasing the sampling rate. BCH codes are widely been used for error detection and correction. The generated check bits of the BCH encoder are appended with the message bits to form a codeword. This codeword is sent to the receiver to detect any error during the transmission. One of the main components of BCH encoder is LFSR (Linear Feedback Shift Register). LFSR find its wider application in Built-in-Self-Test, signature analyzer etc. , whereas