Self-Test Techniques in SoC for Low Power Consumption

A generic built-in self-test needed for SoC devices implementing for low power consumption. In this we proposed a new technique to generate a fully pre-computed test set in a deterministic BIST using simple gray counter within a reasonable clock cycles. Conversely, we consider only a small part of the circuit which is to be tested is active and the other parts of the circuit are fed with low leakage input patterns. After that every CUT is fed by a gray counter which makes the overall consumption extremely low. Here we combine this BIST with the external testing Strategy for low power consumption using slow-testers. That all concurrent operations are performed in less number of clock pulses. We also consider the SoC devices for the test in the consumption by reducing the number of transitions using a gray counter which stores only one bit during the clock cycle. This approach requires nominal hardware overload over pseudorandom BIST using LFSR or CA.