Design of Low Power Baugh Wooley Multiplier Using CNTFET
نویسندگان
چکیده
Multipliers are one of the most important components in microprocessors and DSP processors [9]. Baugh Wooley is one among them and it is an array multiplier. Array multipliers have a more regular layout and it presents high speed performance. The paper deals with the design of a Baugh Wooley multiplier using Carbon Nanotube Field Effect Transistor (CNTFET). A Verilog-A formulation of the Stanford compact model for CNTFET is used for simulation of Multiplier in Cadence circuit simulator. CNTFET based multipliers are energy efficient. Since multipliers are the important component of almost all processors they must be fast and less power consuming.
منابع مشابه
FPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared wi...
متن کاملAn Efficient Baugh-Wooley Multiplication Algorithm for 32-bit Synchronous Multiplication
This paper presents an efficient implementation of a high speed 32-bit synchronous Baugh-Wooley multiplier using the Brent-Kung. BW multiplier involves basic operations of generation of partial product and their accumulation. As a result of which they occupy less area and provides fast speed as compared to the serial multiplier. This is very important criteria because in the fabrication of chip...
متن کاملDesign of a low power high speed 4-2 compressor using CNTFET 32nm technology for parallel multipliers
In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...
متن کاملA High Speed Low Power Modulo 2+1 Multiplier Design Using Carbon-nanotube Technology
Modulo 2+1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this paper, a new circuit implementation of a high-speed low-power modulo 2+1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the fina...
متن کاملDesign of a low power high speed 4-2 compressor using CNTFET 32nm technology for parallel multipliers
In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...
متن کامل