300 mm Lithography and Bonding Technologies for TSV Applications in Image Sensor and Memory Products

Technology advances such as 3-D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what’s currently possible for many production processes, including lithography processes and wafer bonding. There is still the need to coat, pattern and etch structures. This paper will explore some of the lithographic challenges and wafer bonding techniques as used in the 3D Packaging and will describe all the challenges and available solutions. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps. Introduction The expanding consumer electronics market is clearly driving the development of today’s semiconductor innovation. The push for integration, reduction in power consumption and the need for smaller form factors lead to new architectures which combine dissimilar technologies and lead to creative packaging methods, where maximum functionality is packaged into minimal space. So 3D Integration is considered the next generation packaging solution. Today different 3D packaging approaches like SiP (System in Package), SoC (System on Chip) and SoP (System on Package) have been developed in order to answer the requirements for smaller footprint, shorter interconnects and higher performance. SiP “System in a Package” is a functional system or subsystem with multiple wire-bonded or flip-chip dies in an IC package. Other components are placed on the motherboard, like passives, SAW/BAW filters, pre-packaged ICs, connectors and micromechanical parts. This technology enables a stacked chip package with reduced form factor. SoC (System on Chip) integrates all the different functional blocks, like processor, embedded memory, logic core and analog in a monolithic way. These blocks are required to integrate the system design on a single semiconductor chip. SoC designs usually consume less power and have a lower cost and higher reliability than the multichip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well. SoP (System on Package) uses through-vias and high density wiring in order to achieve a higher miniaturization. It is an emerging microelectronics technology that places an entire system on a single chip-size package. Where “systems” used to be bulky boxes housing hundreds of components, SoP saves interconnection time and heat generation by enabling a full system with computing, communications, and consumer functions all in a single chip [1] [2]. Through Silicon Via (TSV) has evolved as one of the key technologies for 3D integration and wafer level packaging. 3D TSV has the potential to one day replace wire bonding and thus enable further size and cost reduction and increase the performance of the device. Today 3D TSV technology has become critical to the growth of 3D components integration, like memory stacking, or for MEMS structure packaging. The first application which is using TSV as mainstream technology is the packaging of CMOS image sensors (CIS). For CMOS image sensors, WLP is already an industrial reality. Today, already about 35% of CMOS imager sensors can be found into latest consumer cellphones and notebook cameras are encapsulated in a WL-CSP and this number keeps growing (Fig. 1.) [3] [4]. Figure 1. WLP devices market forecasts [4] The spin-coating, photolithographic and wafer bonding processes which are necessary to create and connect these TSVs will be presented. Also the achieved results and used equipment will be described. Process Flow One of the typical process flows to form TSVs is shown in Figure 2. These steps are required for through silicon via wafer processing. First, the etch mask must be created. This involves coating, exposing and developing the mask. Once the mask is created, the vias can be etched and insulated. Via filling can then be completed using various materials such as copper and tungsten. The fill process is determined by the fill materials. As of today, copper is the most commonly used material for TSVs, but other materials like Tungsten (W) or Cu3Sn alloy are used as well.