Low Power Multiplexer Decomposition - Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on

The advent of portable digital devices such as laptop personal computers has made low power circuit design an increasingly important research area. Recently, low poweT decomposition for simple logic gates such 0s AND and O R has been extensively researched. However, the problem of MUX decomposition to minimize power dissipation has not been addressed. I n this paper, we study the pToblem of low power multiplexer ( M U X ) decomposition. M U X decomposition i s the procedure of transforming an n-to-one MUX into an equivalent tree of two-to-one MUXes. We propose 0 formulation for the minimum power MUX decomposition problem based on the common CMOS pass transistor implementation of 0 M U X . Given the occurrence probabilities of the data signals and their on probabilities, we analyze the power dissipation of OUT MUX implementation and giue 0 general method for computing the power dissipation of 0 MUX tree decomposition. W e then present several algorithms which eficiently generate minimum power MUX decompositions. W e demonstrate the effectivene8s of our algorithms with experimental results.