EFFECTS OF NoC ARCHITECTURAL PARAMETERS IN MPSoC PERFORMANCE
نویسندگان
چکیده
The goal of this end of term work is to evaluate the impact of the Network-on-Chip (NoC) parameters over the performance of applications on Multiprocessors Systems-on-Chip (MPSoCs). Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs. Therefore, the adoption of networks-on-chip (NoCs) is a trend for the communication infrastructure in MPSoCs due to their performance compared to bus-based architectures and scalability compared to crossbar-based architectures. However, we were not able to find any reference in the state-of-the-art evaluating the impact of NoC parameters in the performance of applications running in MPSoCs. This work proposes a simulation-based monitoring method to evaluate network performance. Such monitoring collects performance results for different MPSoC applications scenarios, and for each scenario network parameters such as buffer size, routing algorithm and topology vary. The goal is to correlate NoC parameters with the MPSoC performance. This work adopts the HERMES NoC and the HeMPS MPSoC and tries to answer the following question: “ how does a given NoC parameter affect the performance of the MPSoC?”
منابع مشابه
Dynamic communications mapping in multi-tasks NoC-based heterogeneous MPSoCs platform
Multi-processor system-on-chip (MPSoC) has emerged as a solution to address the increased computational requirements of modern applications. The network-on-chip (NoC) has been introduced as a power-efficient and scalable communication infrastructure between processors. One important phase in architectural exploration in NoC-based MPSoC is the communications mapping. Mapping parallelised communi...
متن کاملFPGA-Based Prototyping and Emulation Framework
The FPGA-Based Prototyping and Emulation Framework, which the researchers developed as part of WP8, can be integrated in the early design process of NoC-based MPSoC architectures. The framework was used to emulate the operation of the MPSoCs developed as part of the project (QAM MPSoC, etc...). The framework consists of a cycle-accurate, high-level NoC simulator and a library of synthesizable h...
متن کاملTransaction Level Model Simulator for NoC-based MPSoC Platform
Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC) architecture is a promising SoC design solution, offering high computational power with lots of flexibilities. However, finding the optimal MPSoC architecture configuration remains an enormous challenge due to its high structural complexity and functional diversity. In this paper, we introduce a Transaction level NoC SIMulator (...
متن کاملA Novel NoC Architecture Framework for 3D Chip MPSoC Implementations
This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC archi...
متن کاملA Layered Architecture for NOC Design Methodology
Multiprocessor system on chip (MPSoC) platform is an innovative trend of System on Chip (SoC) that enhances system performance. Demanding quality of service parameters and performance metrics, especially in mobile applications, are leading to the exploration of even more innovative architectures for SoC. These will have to incorporate highly scalable, reusable, predictable, cost and energy effi...
متن کامل