Area–Time Performances of Some Neural Computations
نویسندگان
چکیده
The paper aims to show that VLSI efficient implementations of Boolean functions (BFs) using threshold gates (TGs) are possible. First we detail depth-size tradeoffs for COMPARISON when implemented by TGs of variable fan-in (∆); a class of polynomially bounded TG circuits having O (lgn ⁄ lg∆) depth and O (n ⁄ ∆) size for any 3 ≤ ∆ ≤ clgn, improves on the previous known size O (n). We then proceed to show how fan-in influences the range of weights and of thresholds, and extend these results to Fn,m, the class of functions of n variables having m groups of ones. We conclude that the fan-in could be used by VLSI designers for tuning the area-time performances of neural chips.
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