Statement Paul V . Gratz

My research in computer architecture focuses on interconnection networks for scalable multi-core and distributed processor microarchitectures. Computer architecture bridges the gap between application and device technology. Application workloads have never been more compute intensive, meanwhile device constraints of power, heat, and reliability have recently forced the computer industry to shift focus from single processor core performance to instantiating multiple processor cores on each chip. As computer architecture enters the era of multi-core, intra-core communication becomes critical to achieve continued increasing system performance. As a graduate student I led the design, implementation and verification for the second level cache and inter-processor network-on-chip (NOC) on the TRIPS processor prototype [2]. Building upon my work on the TRIPS networks-on-chip, my dissertation research explores network utilization efficiency of realistic NOC designs as a means to improve performance and manage power. Looking forward, I plan to focus my future research on closing the expanding gap between application and technology as we move towards chip-multiprocessors (CMPs) with hundreds to thousands of cores. In this statement, I outline the contributions of my dissertation and discuss the direction of my future research.