Design of Extended 4-bit Full Adder Circuit Using Hybrid-cmos Logic

This paper presents a performance analysis of hybrid 1-bit full-adder circuit design. The adder cell is dissected into smaller modules. The modules are analyzed and calculated extensively. To explore good-drivability, noise-robustness, and low-energy operations for deep sub micrometer to explore hybrid-CMOS style design. Hybrid-CMOS design style uses various CMOS logic style circuits to construct new full adders with desired performance .In this paper, a hybrid 1-bit full adder design employing both complementary metal oxide semiconductor (CMOS) logic and transmission gate logic is reported. In the proposed design of this paper first implemented for 1-bit full adder and then extended for 4 bit full adder circuit. The extended 4-bit full adder circuit has been implemented by using Tanner EDA (Electronic design automation) tool and so on. The proposed extended 4 bit full adder design is to enhance the speed of the Operation and also reduces the area, and power consumption. The new extended 4-bit fulladder circuit successfully operates at low voltages. Performance parameters such as power consumption, and layout area were compared with the existing 1-bit full adder Designs such as complementary passtransistor logic, transmission gate adder and function-adder, hybrid pass-logic with static CMOS output drive full adder, and so on.