Design and Modeling of 60-GHz CMOS Integrated Circuits

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. As the number of devices supporting high-quality digital multimedia continues to increase, there is a strong desire to transfer the data quickly and conveniently. Wireless transmission offers ease of setup, flexibility of placement, and avoids the need for unsightly and expensive cables. However, today's commercially available wireless systems are incapable of the multi-gigabit/sec data-rates required for this application. The frequency spectrum around 60-GHz is ideally suited for high-speed wireless data transfer, but it has yet to be widely used for consumer applications due to its high implementation costs. Complementary metal-oxide-semiconductor (CMOS) processing is the lowest cost semiconductor technology. As a consequence of the ever-shrinking transistor dimensions, the high-frequency performance of state-of-the-art CMOS technology is improving, and it is becoming an attractive alternative to the expensive compound semiconductor technologies traditionally needed for 60-GHz transceivers. If a 60-GHz CMOS radio can be implemented, this would open up new opportunities for the ubiquitous use of this spectrum for consumer applications. This dissertation explores the challenges involved in designing 60-GHz CMOS circuits. First, the key parasitic components that limit the high-frequency performance of CMOS transistors are identified, and an optimal layout to minimize these parasitic 2 elements is proposed. Second, transistor and passive models are investigated that can provide highly-accurate prediction of the device characteristics up to millimeter-wave (mm-wave) frequencies. This avoids the need to design with unnecessary margin due to modeling uncertainties. Following some basic guidelines, the models can result in simple extensions of commonly-used device models and are verified to be accurate up to 65 GHz. Accurate mm-wave measurements of the devices are necessary in order to extract good models, but the low resistivity of the CMOS substrate presents unique challenges. Different measurement and de-embedding methodologies are evaluated, and an approach to extract the small-signal and noise characteristics of the devices is presented and validated. Finally, mm-wave amplifiers and filters are fabricated in a 130-nm bulk digital CMOS technology to demonstrate the effectiveness of the device design and modeling methodology. This results in the …