Design and Implementation of Offset Error Cancelling Using High Speed Flash Adc
نویسندگان
چکیده
The performance of Flash Analogto-Digital converter is greatly influenced by the choice of Comparator and Thermometer-toBinary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment using spectre simulator under 90nm technology. The pre simulation results for the design shows a low power dissipation of 87uw for the comparator and 1.05mW and 1.984mW power dissipation for 3-bit and 4-bit Flash ADC respectively. The circuit operates with an input frequency of 25MHz and 1.5V supply with a conversion time of 2.162ns and 6.182ns for 3-bit and 4-bit ADC respectively.
منابع مشابه
Efficient error-cancelling algorithmic ADC
An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represen...
متن کاملA 1gsample/s 6-bit Flash A/d Converter with a Combined Chopping and Averaging Technique for Reduced Distortion in 0.18µm Cmos
A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18μm CMOS (May 2005) Nikolaos Stefanou Chair of Advisory Committee: Sameer Sonkusale Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-t...
متن کاملA 6-bit, 1-GHz Flash ADC in 0.35μm CMOS
+ Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, B-3001 Heverlee, [email protected] . Abstract The design plan and measurement results of a very high-speed 6 bit CMOS Flash ADC converter are presented. The very high acquisition speed is obtained by improved comparator design. At these high frequencies power-efficient error correction logic is necessary. Measurements show th...
متن کاملDesign and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary
The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of lo...
متن کاملFat Tree Encoder Design for Ultra-high Speed Flash A/d Converters
The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the authors presented the fat tree thermometer codeto-binary code encoder that is highly suitable for the ultrahigh speed flash ADCs. The simulation and the implementation results show that the fat tree encoder outperforms the commonly used ROM encoder in terms of speed and p...
متن کامل