Negotiated A* Routing for FPGAs

In the next few years, logic capacities for fieldprogrammable gate arrays are expected to exceed one million gates per device. While this expansion of FPGA device resources offers the promise of exceptional finegrained performance for developing technologies such as ASIC prototyping and FPGA computing, supporting computer-aided design tools have yet to be developed to target these devices rapidly and efficiently. This paper addresses the compilation time issue for routing array FPGAs with segmented routing architectures. By treating the routing problem as an A∗ search, it is possible to trade additional device routing resources for decreased router run-time by converting an exhaustive breadth-first maze route into a shorter depth-first route. It is shown that for the depth-first case, the sparse nature of FPGA routing switches in commerical architectures, such as the Xilinx XC4000 family, necessitates an additional localized search near net inputs, called domain negotiation, to aid in directing the route of each design net onto a set of routing resources most likely to lead to a successful route. For a set of large FPGA benchmarks, a route time speedup of over an order of magnitude for an iterative maze router configured for depth-first routing is shown when compared to the same router configured for a breadth-first search.