A 22-mW 435-MHz differential CMOS high-gain LNA for subsampling receivers

A low-power, high-gain CMOS low noise amplifier (LNA) for use as the first stage of a subsampling receiver is proposed. The performance of +96-dB voltage gain and less than 1-dB Noise Figure (NF) with very low power consumption is reported for the first time and makes it suitable for subsampling mixer with Track and Hold (T/H) circuit. The LNA contains both tuned and inductorless amplifier stages. The first stage utilizes optimum transistor gate width-length ratio (W/L), improved-Q on-chip spiral inductors, fully differential architecture, and current-reuse technique to achieve low-noise, high-gain, and low-power at the same time. The following stages are inductorless amplifiers designed to achieve the maximum-gain. Cascode transistors are used in all stages to maintain reasonable gain at high frequencies and to achieve good reverse isolation. The amplifier linearity is sacrificed as a consequence of its high gain.