Based FPGA Synthesis for Multi - Output Boolean Functions
نویسندگان
چکیده
| One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f = (f 1 ; : : : ; f m ) : f0; 1g n ! f0; 1g m have to deal with is nding sublogic which can be shared by di erent outputs, i.e., nding boolean functions = ( 1 ; : : : ; h ) : f0; 1g p ! f0; 1g h which can be used as common sublogic of good realizations of f 1 ; : : : ; f m . In this paper we present an e cient robdd based implementation of this Common Decomposition Functions Problem (cdf). Formally, cdf is de ned as follows: Given m boolean functions f 1 ; : : : ; f m : f0; 1g n ! f0; 1g, and two natural numbers p and h, nd h boolean functions 1 ; : : : ; h : f0; 1g p ! f0; 1g such that 81 k m there is a decomposition of f k of the form f k (x 1 ; : : : ; x n ) = g (k) ( 1 (x 1 ; : : : ; x p ); : : : ; h (x 1 ; : : : ; x p ); (k) h+1 (x 1 ; : : : ; x p ); : : : ; (k) r k (x 1 ; : : : ; x p ); x p+1 ; : : : ; x n ) using a minimal number r k of single-output boolean decomposition functions. Experimental results applying the method to FPGA synthesis are promising.
منابع مشابه
Based FPGA Synthesis for Multi - Output
1 Communication Based FPGA Synthesis for Multi-Output Boolean Functions Christoph Scholl Paul Molitor Department of Computer Science Department of Computer Science Universit at des Saarlandes Martin-Luther Universit at Halle D 66041 Saarbr ucken, FRG D-06099 Halle (Saale), FRG Tel: ++49 681 302-2274 Tel: ++49 345 622 529 Fax: ++49 681 302-4421 Fax: ++49 345 622 514 e-mail: [email protected]...
متن کاملEecient Robdd Based Computation of Common Decomposition Functions of Multi-output Boolean Functions
One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f =
متن کاملMapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching
To support FPGA synthesis in the OAGear package, we have implemented the following new components: (i) a cut-based technology mapper for LUT-based FPGA with delay/area optimization options, (ii) an efficient SAT-based Boolean matcher (SAT-BM) for both single-output and multipleoutput Boolean functions, and (iii) an area-aware resynthesis algorithm using this SAT-BM. The SAT-BM incorporates the ...
متن کاملPreprint from Workshop Notes, International Workshop on Logic Synthesis (IWLS’97), Tahoe City, California, May 19-21, 1997 Multi-output Functional Decomposition with Exploitation of Don't Cares
Functional decomposition is an important technique in logic synthesis, especially for the design of lookup table based fpga architectures. We present a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals: the minimization of the numbers of decomposition functions in the current decomposition step and the extraction o...
متن کاملCommunication based multilevel synthesis for multi-output Boolean functions
A multilevel logic synthesis technique for multi-output boolean functions is presented which is based on minimizing the communication complexity. Unlike the approaches known from literature [1, 5, 6, 8] which in the nal analysis decompose each single-output function f i of a multioutput function f = (f 1 ; . . . ; f m ) independently of the other single-output functions f j (j 6= i), the approa...
متن کامل