LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family

|In this paper we present a Low Voltage Diierential Current Switch Logic (LVDCSL) gate which is capable of achieving high performance for large fan-in gates. High fan-in is enabled by allowing large stacked NMOS tree heights using a pre-discharged NMOS tree, at the same time the power penalty of an increased number of internal nodes in the gate is mitigated by restricting internal node voltage swings. It is topologically a Cascode Voltage Switch Logic Gate with a cross-coupled inverter based load. However, unlike other DCVS gates with cross-coupled inverters, it is fairly robust and relatively insensitive to load imbalances at the output. The salient features of this low-voltage DCSL family are: high speed for high fan-in large stack height NMOS trees, low power due to restricted internal voltage swings and a latching nature which locks out inputs once outputs are evaluated. While the gate exhibits spikes at its diierential outputs (in common with other sense-amp based CVSL logic gates such as SSDL) transitions are greatly reduced simplifying interface to conventional CMOS circuits. Our results show that LVDCSL is capable of working at under 2volts in a 0:35 CMOS process while being faster than comparable Domino gates. At the same time total power consumption is reduced. LVDCSL achieves 40% delay improvement and 22% power reduction in comparison with Domino gates for 8 bit carry lookahead circuits. The eeect of changing circuit parameters on the energy-delay performance of LVDCSL is presented. Results for the critical path of an adder, reveal that the complexity aaorded by the gate, eeectively decreases the number of logic levels and leads to improved performance.