Overview of the Pipe Processor Implementation

The PIPE processor is an outgrowth of the PIPE Project, a research project at the University of Wisconsin-Madison whose goal was to investigate computer architectures that would be well suited to VLSI implementation. The implemented PIPE processor is a 32-bit pipelined single chip processor with a simplified load-store instruction set, a 5 stage pipeline, a two-cycle ALU, and the following unique features: (1) Architectural I/O queues that lie between the processor internals and the external memory. These queues are used to reduce the impact of memory delays on processor performance. (2) A delayed branch scheme that allows the compiler to specify the number of instructions after a branch that will be unconditionally executed (between 0-7) based on how well it was able to schedule code. (3) A sophisticated instruction fetch mechanism featuring a small on-chip instruction cache, an instruction queue and an instruction queue buffer that together perform as well as a much larger conventional instruction cache. (4) A register file that is divided into foreground and background registers, to improve the performance of subroutine calls. Extensive simulations of the original design indicated that the features listed above provide significant performance improvements. However, it was felt that this combination of architectural features was sufficiently unique to justify an actual implementation of the processor, to investigate whether they would work as well in practice as in theory. The processor was fabricated by MOSIS in 1.5 micron nMOS, and is 2-3 times faster than the 1.5 micron nMOS versions of the RISC and MIPS chips. This improved performance is due in large part to the presence of the I/O queues, which allow the processor internals to run at a clock rate completely independent of the external memory speed. Many other valuable lessons were learned from the implementation, and a number of new questions have been generated whose resolution is still under investigation. We feel that the benefits from implementing the processor have definitely been worth the effort.