Multi-level Digital/mixed-signal Simulation with Automatic Circuit Partition and Dynamic Delay Calculation

A unified and consistent representation of logic gates at logic and circuit levels is described based on the subcircuit expansion approach. A dynamic-delay model is proposed for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering on the delay. It is shown that the approach provides near circuit-level accuracy with gate-level speed and is useful for accurate timing simulation of digital and mixed-signal VLSI circuits.