Configuring a Load-Balanced Switch in Hardware (Hot Interconnects 2004)

The load-balanced switch architecture is a promising way to scale router capacity. We explained in [1] how it can be used to build a 100Tb/s router with no centralized scheduler, no memory operating faster than the line-rate, no packet missequencing, a 100% throughput guarantee for all traffic patterns, and an optical switch fabric that simply spreads traffic evenly among linecards. This switch fabric uses optical MEMS switches that are reconfigured only when linecards are added and deleted, allowing the router to function when any subset of linecards is present and working. In [2] we introduced a configuration algorithm that will find a correct configuration of the MEMS switches in polynomial time. However, we found that our algorithm takes over 50 seconds to run in software for a 100Tb/s router. Our goal is to restore the router to operation within 50ms upon failure. So we modify our algorithm for implementation in dedicated hardware. In particular, to simplify the Ford-Fulkerson algorithm in bipartite matches, we reduce memory accesses and use bit manipulation schemes. Then, we decompose permutations using the SlepianDuguid algorithm and reduce the configuration time with a simplified memory scheme. Our experimental results show that it is possible to achieve the 50ms target.