Sensitivity Study of Interconnect Variation Using Statistical Experimental Design

We present a sensitivity study approach to evaluate the effects of interconnect variations on the performance of large, complicated circuits. The approach uses highly efficient designed experiments. The results from the study of a multiplier circuit are presented as an example. 1.0 Introduction TodayÆs submicron circuits require a sensitivity study of interconnect variation on circuit performance in order to understand the effect of process variation, and thus help optimal circuit and process design. In [1], we developed an approach which uses parameterized interconnect models to study the circuit sensitivity to interconnect parameter variations. In this approach, all interconnect wires of a circuit were modeled via closed form analytical models. There were several advantages to this approach. Firstly, it made the sensitivity study much easier without going through the time-consuming and error-prone process of whole chip circuit extraction. Secondly, when studying the effect of the spatially distributed variations, this approach worked well since interconnect wires can be modeled separately using different models at different positions. Thirdly, the sensitivity to layout parameters can be easily evaluated via this approach. Fourthly, when studying a complicated large circuit such as a microprocessor, some simple circuits that may represent the behavior of a microprocessor can be analyzed using the above approach. In such a way, we can evaluate and forecast the performance spread of the microprocessor resulting from interconnect parameter variations before the manufacturing of the product die. However, there were several limitations to that approach. It required manual construction of an RC model for each interconnect wire, so it was not very suitable for studying a complicated circuit with irregular interconnect structures. It would be inefficient to manually model the interconnect wires of a whole circuit. However, such sensitivity study of a real circuit is often important in order to reduce the performance spread, especially for high performance circuits. In this work, a new, efficient approach is developed to study the impact of interconnect technology parameter variations on circuit performance.