Characterization of Stress and Topology in Wlp Processes Using Cgs Interferometry

Wafer Level Packaging (WLP) is a key component of the 3D Packaging roadmap. It expands low cost wafer-level processing to advanced packaging by delivering improved density, higher performance in a small form factor. Foundries and OSATs are investing rapidly in WLP. As with any new packaging application, WLP will be required to demonstrate mature yield levels for cost effective high volume manufacturing. Planarity has become one of the top yield detractors and assembling large surfaces with micronscale features requires new manufacturing capabilities. Using a full-wafer Coherent Gradient Sensing (CGS) interferometer it is possible to image precisely the surface of the WLP wafer, capturing the whole topography with three million pixels at a speed greater than 100 wafers per hour. This paper will discuss the application of the Superfast 3G system, the first production 3D WLP Macro Inspection System developed for volume manufacturing of patterned wafers. Its self-referencing interferometer allows the inspection to be made on any type of surface or films stack, and does not require a measurement target. By comparing the topography evolution between steps, planarity variations as well as stress can be measured and controlled. Given an established WLP process flow with a high mix of products, the inspection system enables rapid understanding of wafer level, die level and within die topography and stress challenges. In a foundry environment where the product layout (e.g. TSV, RDL, micro-bumps) and the planarity and stress specifications will vary, The system allows customized Statistical Process Control (SPC) of each individual production batch. This paper will discuss specific examples to demonstrate how planarity and stress process control can be put in place to insure that each product yields reliably.