Exploiting Modularity for Synthesis and Verification of Supervisors

Efficient algorithms for synthesis and verification of supervisors in the Supervisory Control Theory framework are presented. The presented algorithms solve the controllability problem. In many real-world applications both the plant and specification is given as a set of interacting automata or processes. In this work, we exploit this modular structure to reduce the computational effort. First, we present an algorithm that verifies if a given supervisor is controllable with respect to a plant. Second, we show how to synthesize a set of modular supervisors that while interacting with the original supervisors guarantees that the closed system is controllable. Third, we show how the verification algorithm can be used as an efficient language inclusion algorithm. The presented algorithms are benchmarked on a real-world application.