Reducing cache and TLB power by exploiting memory region and privilege level semantics

1383-7621/$ see front matter 2013 Elsevier B.V. A http://dx.doi.org/10.1016/j.sysarc.2013.04.002 q This is an extension of paper ‘‘Reducing L1 Caches Semantics’’, published in International Symposium o Design (ISLPED), July 30 – August 1, 2012. Compared material in this sumission mainly includes: optimiz detailed analysis on the counter-intuitive phenomen by kernel code; detailed analysis on cache occupan accesses with different semantics; evalua tion benchmarks; sensitivity studies including SMT, OoO This work was done when all authors were employed ⇑ Corresponding author. Tel.: +1 5037506614. E-mail address: [email protected] (Z. Fang). The L1 cache in today’s high-performance processors accesses all ways of a selected set in parallel. This constitutes amajor source of energy inefficiency: atmost one of theN fetched blocks can be useful in anN-way set-associative cache. The other N-1 cachelines will all be tag mismatches and subsequently discarded. We propose to eliminate unnecessary associative fetches by exploiting certain software semantics in cache design, thus reducing dynamic power consumption. Specifically, we usememory region information to eliminate unnecessary fetches in the data cache, and ring level information to optimize fetches in the instruction cache.We present a design that is performance-neutral, transparent to applications, and incurs a space overhead of mere 0.41% of the L1 cache. We show significantly reduced cache lookupswith benchmarks including SPEC CPU, SPECjbb, SPECjAppServer, PARSEC, and Apache. For example, for SPEC CPU 2006, the proposed mechanism helps to reduce cache block fetches from the data and instruction caches by an average of 29% and 53% respectively, resulting in power savings of 17% and 35% in the caches, compared to the aggressively clock-gated baselines. 2013 Elsevier B.V. All rights reserved.