Optimization of Delay-Insensitive Circuits { a Case Study

abstract We explore ways of constructing eecient delay-insensitive (DI) networks from a set of primitive DI elements by means of a case study. Several approaches that improve on recent designs of a modulo-N counter in the literature are illustrated. We obtain low constant latency, low constant response time, constant power consumption and optimal area-complexity designs for this circuit. For moderately large N, the area complexity compares well even with standard designs under synchronous (clocked) discipline. Many of these eeciencies derive from the exploitation of the powerful property of timing-independent composability of DI circuits.