Signature Analysis and Test Scheduling for Self-Testable Circuits

Usually in complex circuits the lest execution is divided into a number of subtasks. each producing a signature in a self-test register. These signatures innueocc one another. In this paper il is shown how test schedules can be can· strutted, in order to minimize the number of signatures to be evaluated. The error masking probabilities decrease, when the subtasks of the test execution are repeated in an appropriate order, and an equilibrium situation is reached where the error masking probabilities arc minimal. A method is presented for consuucting test schedules such that only the signatures at the primary outputs must be evaluated to gel a sufficient fault coverage. Then no inter· nal scan path is required, only few signatures have to be evaluated at the end of the test execution, and the test control at chip and board level is Simplified. The amount of hardware to implement a built·in self-test is reduced significantly.