Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme
نویسنده
چکیده
A register that is designed to allow the bits of its contents to be moved to left or right is known to be a shift register. Shift registers may be implemented by using pulsed latches and flip flops.However,shift register implemented by pulsed latches have power and area problems .So, flip flops are preferred over pulsed latches. In this paper, a VLSI architecture for low power area efficient VLSI architectures for shift register using explicit pulse triggered flip flop based on signal feed-through scheme is proposed. The performance of the proposed shift register is compared with that of the shift register implemented by using pulsed latches. From the experiments and the results obtained it is observed that the proposed shift register is having less area and low power when compared to the shift register using pulsed latches with 79.83% and 99.26 % for an N-bit shift register. All the Simulation results,schematic and Layouts are based on CMOS 90nm technology in HSPICE tool,Digital schematic tool (DSCH) and Micro-wind 3.1.
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