Placement and Placement Driven Technology Mapping for FPGA Synthesis

Because of the more restrictive placement and routing constraints in Xilinx FPGA designs, conventional physical design tools for general placement and routing architectures usually do not work well for FPGA designs. Moreover, to generate high quality circuits which are easy to place and route, it is important to consider the specific physical design constraints during the technology mapping process. In this paper, we first present a performance driven placement algorithm specifically developed for the Xilinx FPGAs. We then present a new placement driven technology mapping algorithm which uses placement information to guide the mapping process.