Motif parameters based characterization of line edge roughness(LER) of a nanoscale grating structure
نویسندگان
چکیده
Motif parameters were introduced to characterize LER of a nanoscale grating structure. Firstly with electron beam lithography employed the expected nano-scale grating structure with linewidth 16nm was fabricated on positive resist. Then the line edge profiles of the structure were extracted and their LER was characterized. The results showed aforementioned evaluation method is rather simple, effective and recommendable.
منابع مشابه
Mueller matrix ellipsometry of artificial non-periodic line edge roughness in presence of finite numerical aperture
We used azimuthally-resolved spectroscopic Mueller matrix ellipsometry to study a periodic silicon line structure with and without artificially-generated line edge roughness (LER). The unperturbed, reference grating profile was determined from multiple azimuthal configurations using a generalized ellipsometer, focusing the incident beam into a 60 μm spot. We used rigorous numerical modeling, ta...
متن کاملAnalysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs
We present a full-3D statistical analysis of line edge roughness (LER) in sub0.1 μm MOSFETs. The modelling approach for line edges and the parameters used in the analysis take into account the statistical nature of the roughness. The results indicate that intrinsic fluctuations in MOSFETs due to LER become comparable in size to random dopant effects and can seriously inhibit scaling below 50 nm.
متن کاملIntrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness
In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation exper...
متن کاملComprehensive Standard Cell Characterization Considering Random Line-Edge Roughness Lithography Variation
As the transistors are scaled down, undesirable performance mismatch in identically designed transistors increases and hence causes greater impact on circuit performance and yield. Since Line-End Roughness (LER) does not decrease as the device shrinks and has been reported to be in the order of several nanometers, it has evolved as a critical problem in the sub-45nm devices and may lead to seri...
متن کاملStudy of Gate Line Edge Roughness Effects in 50 nm Bulk MOSFET Devices
We studied gate line edge roughness (LER) and its effect on electrical characteristics of 50nm bulk MOSFETs. Using simulation, we studied the underlying mechanism of three significant LER effects on the electrical performance of advanced 50 nm gate length bulk devices. First, we found that off-state leakage current is much more sensitive than the on-state drive current to gate LER. Second, we f...
متن کامل