In 8: Conclusions

order to support the MMU and cache the processor will require a coprocessor interface. This is the major feature of the ARM6 which is missing on AMULET1. The ARM6 coprocessor interface is synchronous and inappropriate for asynchronous use, so a new interface will be developed. The MMU and cache will be based on existing ARM designs for architectural compatibility, but will be enhanced for asynchronous applications by pipelining where appropriate. Taken branches have a high latency cost on AMULET1, so various history and trace techniques are currently under investigation to establish their applicability to asynchro-nous pipelined processors. It is not yet clear whether such techniques will be cost-effective on a successor design. The AMULET1 design demonstrates the feasibility of developing complex asynchronous circuits. The design encompasses many of the more complex features of modern high-performance RISC processors, such as exact exception handling, instruction set compatibility and pipe-lined operation, and shows that asynchronous techniques are applicable to commercial scale digital design tasks. AMULET1 is within a factor 2 of the ARM6 with respect to important parameters such as performance, power consumption and die size. As such it demonstrates that asynchronous designs are comparable with clocked designs, but AMULET1 does not, at this stage, demonstrate any significant advantage over its clocked predecessors. It should be borne in mind, however, that ARM6 is a highly evolved fourth generation synchronous processor, whereas AMULET1 is the first of its line. Furthermore, many features of the ARM instruction set have been designed with reference to its synchronous implementation ; these have been sources of difficulty in the asynchro-nous implementation and bias the comparison unfavourably against AMULET1. Work is still going on to enhance the design and substantial improvements are possible in many areas. It is hoped that in the near future we will be able to demonstrate real advantages for asynchronous methodologies based on the techniques outlined in this paper.