Decoupled Sectored Caches

Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for crating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Abstract Maintaining a low tag array size is a major issue in many cache designs. In the decoupled sectored cache we present in this paper, the monolithic association betwewen a cache block and a tag location is broken; the address tag location associated with a cache line location is dynamically chosen at fetch time among several possible locations. The hit ratio for a decoupled sectored cache is very close to the hit ratio for a non-sectored cache. Then a decoupled sectored cache will allow the same level of performance as a non-sectored cache, but at a signiicantly lower hardware cost.