An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays

| Rapid system prototyping is one of the main applications for eld-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design speci cations can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout recon guration algorithm is proposed for FPGAs. In layout recon guration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to recon guration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the e ectiveness and e ciency of the algorithm.